1. Field of the Invention
The present invention relates to a phase adjusting function evaluating method, a transmission margin measuring method, an information processing apparatus, a program and a computer readable information recording medium.
2. Description of the Related Art
FIG. 1 shows a block diagram illustrating a configuration of a transmission chip and a reception chip in one example of the related art.
These transmission chip 100 and reception chip 200′ are silicon chips configuring a semiconductor integrated circuit applied to, for example, a part of a computer system, described later with reference to FIG. 5, which part carries out data transmission between a system board 1-i and a memory system interconnect 3, or between the memory system interconnect 3 and an IO unit 2-i. 
The transmission chip 100 includes a phase synchronization circuit (PLL) 110, a clock output circuit 115, data output circuits 141-1 through 141-n (which may be typically referred to as 141-i), data selecting circuits 121-1 through 121-n (which may be typically referred to as 121-i).
The data selecting circuit 121-i selects one of regular data and a training pattern, and provides the selected one to the data output circuit 141-i. 
The training pattern is a data sequence predetermined between the transmission chip 100 and the reception chip 200′, and is used for initial phase adjustment operation, which will be described later.
The reception chip 200′ includes a clock input circuit 210, data input circuits 221-1 through 221-n (which may be typically referred to as 221-i), phase adjusting circuits 231′-1 through 231′-n (which may be typically referred to as 231′-i), flip-flop circuits 241-1 through 241-n (which may be typically referred to as 241-i), and pattern detecting circuits 251-1 through 251-n (which may be typically referred to as 251-i).
As shown in FIG. 2, the phase adjusting circuit 231′-i includes a delay line (DL) 30, a phase detecting circuit 20 and a control part 10.
The delay line 30 provides a delay amount to an input clock signal, which delay amount is determined by a pointer (TAP value) stored in a register of the control part 10. As a result of the delay amount being controlled by means of the TAP value, a phase of the input clock signal is controlled accordingly.
The phase detecting part 20 detects a phase relationship between the input clock signal and input data, and directs a control part 10 to increase/decrease the TAP value 11.
The control part 10 thus updates the TAP value 11 according to a directive provided by the phase detecting circuit 20.
As shown in FIG. 3, the pattern detecting circuit 251-i includes a pattern detecting part 90 and a control part 80.
When the pattern detecting circuit 251-i detects the above-mentioned training pattern in the pattern detecting part 90 upon the initial phase attunement operation, it generates a predetermined detection flag 81, and holds it in the control part 80.
Below, phase adjustment operation in the reception chip 200′ configured as mentioned above will be described.
In data transmission between the transmission chip 100 and the reception chip 200′, in order to ensure a margin (referred to as a transmission margin, hereinafter) in taking data with the clock signal in the flip-flop circuit 241-i in the reception chip 200′, input to the flip-flop circuit 241-i should be made in such a timing relationship that a falling edge of the clock signal occurs at the center of the data waveform (see FIG. 4).
Immediately after a power supply is started up, such a phase relationship may occur between the clock signal and the data that proper data transmission may not be achieved. Therefore, the above-mentioned training pattern known to both the transmission chip 100 and the reception chip 200′ is used first to establish a proper phase relationship. Phase adjustment operation for establishing the proper phase relationship between the clock signal and the data is called the initial phase adjustment operation.
Upon the initial phase adjustment operation, the data selecting circuit 121-i selects the training pattern, and outputs the same.
In the reception chip 200′, the clock signal input via the clock input circuit 210 from the transmission chip 100 and the data of the training pattern input via each data input circuit 221-i are input to the phase detecting part 20 of the phase adjusting circuit 231′-i, which determines a phase adjusting direction.
FIG. 4 shows a time chart illustrating the phase adjustment operation carried out by the phase detecting part 20.
With a rising edge of the data shown in FIG. 4 (a), an H/L (high/low) level of the clock signal shown in FIG. 4 (b) is sampled. When the sampled level is an H level as shown in FIG. 4 (b), a phase is adjusted in such a direction that the clock signal is delayed, as shown in FIG. 4 (c). On the other hand, when the sampled level is an L level as shown in FIG. 4 (d), a phase is adjusted in such a direction that the clock signal is advanced, as shown in FIG. 4 (e). For achieving such a specific phase control, the TAP value 11 of the control part 10 is automatically increased or decreased. As a result, as shown in FIG. 4 (c) or (e), the phase between the data and the clock signal is adjusted in such a manner that a falling edge of the clock signal occurs at the center of the data waveform.
The above-mentioned training pattern has a finite length, and the initial phase adjustment operation is finished when the entire training pattern has been transmitted.
Success or failure of the initial phase adjustment operation is determined with the pattern detection flag 81 held in the control part 80, which pattern detection flag 81 is generated by the pattern detecting part 20 of the pattern detecting circuit 251-i. 
When the phase adjustment results in success, i.e., the falling edge of the clock signal occurs at the center of the data waveform as described above with reference to FIGS. 4 (c) and (e), the flip-flop circuit 241-i can properly takes the data with the clock signal, and thus, the training pattern transmitted from the transmission chip 100 can be properly detected by the pattern detecting part 90 of the pattern detecting circuit 251-i. In this case, the pattern detecting part 90 generates the pattern detection flag 81, which is then held by the control part 80.
On the other hand, when the proper phase adjustment is not achieved by some cause, the data is not properly taken by the flip-flop circuit 241-i, and thus, the training pattern transmitted from the transmission chip 100 is not properly detected by the pattern detecting part 90 of the pattern detecting circuit 251-i. In this case, the pattern detecting part 90 does not generate the pattern detection flag 81.
The pattern detection flag 81 thus held in the control part 80 in the case of the proper phase adjustment, is taken by an external controller not shown, by a function of an external firmware 280′. As a result, the external controller recognizes that the initial phase adjustment operation carried out by each phase adjusting circuit 231′-i results in success. On the other hand, no pattern detection flag 81 is held in the control part 80 in the case where the proper phase adjustment cannot be made, and thus, no pattern detection flag 81 is taken by the external controller in this case. As a result, in this case, the external controller recognizes that the initial phase adjustment operation carried out by each phase adjusting circuit 231′-i results in failure.
When some trouble has occur in the delay line 30, the phase detecting part 20 or the control part 10 in the phase adjusting circuit 231′-i, the phase adjusting function of the phase adjusting circuit 231′-i cannot be carried out, and thus, the proper phase adjusting operation cannot be carried out. In such a case, an operation failure may occur depending on a condition of the ambient temperature, a power supply voltage, frequency, interconnect wiring lengths, or such. Therefore, in such a case where the phase adjusting function of the phase adjusting circuit 231′-i cannot be carried out, this fact should be detected to be solved as soon as possible.
Thus, phase adjustment operation carried out by the phase adjusting circuit 231′-i is such that the phase relationship between the data and the clock signal is automatically optimized. In this connection, there may occur a necessity to know the transmission margin when the optimization is made. In this case, a so-called transmission window (described later with reference to FIG. 13) should be measured. In measurement of such a transmission window in the related art, an oscilloscope is used, and a waveform is observed for each signal therewith. Therefore, a considerable time may be required for the measurement for all the signals when the number of signal lines is large.
Japanese Patent No. 2541186, Japanese Laid-Open Patent Application No. 61-292278 and Japanese Laid-Open Patent Application No. 7-283819 disclose related arts.